1. Field of the Invention
The present invention relates generally to computer memory architecture. More specifically, the present invention relates to a technique to improve the buffer efficiency of hybrid memory systems.
2. Description of the Related Art
There are a large number of different types of memories available for user in computer systems. Random Access Memory (RAM) is typically a fast-access memory that is used for frequent memory reads and writes in a computer system. Common types of RAM include Dynamic RAM (DRAM), Static RAM (SRAM), spin-torque transfer memory random access memory (STT-MRAM) and Phase Change Memory (PCM), among others. RAM is vital for all forms of computing today, from small devices to large data centers.
Each memory type has its advantages and disadvantages in terms of latency/performance, capacity, energy usage, etc. For example, PCM is non-volatile (i.e., it maintains its contents when power is interrupted), whereas DRAM is volatile. PCM also has better scalability than DRAM. DRAM, however, has significantly better write speeds, and slightly better read speeds than PCM. In other words, PCM has longer access latency. PCM also uses more energy when writing, and has limited write endurance. As such, one must sacrifice the advantages of one type of memory when using another type of memory instead. What is needed is a solution that addresses these issues.